This invention relates to electronic device fabrication processes, apparatuses and systems. In particular embodiments, it relates to dielectric gap fill processes, apparatuses and systems.
It is often necessary in semiconductor processing to fill high aspect ratio gaps with insulating material. This is the case for shallow trench isolation (STI), inter-metal dielectric (IMD) layers, inter-layer dielectric (ILD) layers, pre-metal dielectric (PMD) layers, passivation layers, etc. As device geometries shrink and thermal budgets are reduced, void-free filling of narrow width, high aspect ratio (AR) features (e.g., AR>6:1) becomes increasingly difficult due to limitations of existing deposition processes.
New methods, apparatuses, systems and technologies for dielectric gap fill are discussed herein.